Without limiting the scope of the invention, the background of the invention is described in connection with the "SPARC" reduced instruction set computer (RISC) architecture, as an example.
Heretofore, in this field, branch decisions have been based on ALU output status signals or condition codes ALU=0, ALU overflow, ALU output negative, and ALU carry-out. In typical prior art architectures, the ALU produces these status signals at about the same time it can produce its sum output. In highly optimized prior art branch decision circuits, the branch decision or jump-taken signal is produced within five or six gate delays from availability of these status signals. Further delay in prior art "SPARC" branch decision circuits is incurred in computation of the alu-overflow status signal, which is a logical OR of the arithmetic overflow and tagged overflow (a feature specific to the "SPARC" architecture). This logical OR adds an additional gate delay. Still further delay is incurred in prior art branch decision circuits due to the "SPARC" architecture's definition of alu-carryout polarity. The "SPARC" architectures defines the polarity of the carry-out signal to be reversed upon subtract operations relative to the polarity for add operations. This need necessitates a logical INVERT when testing for the condition of alu-carryout of a subtract operation. This logical INVERT adds an additional gate delay.
Another source of delay in prior art branch decision circuits designed in accordance with the "SPARC" architecture stems from using a condition code which is set by ALU operations and used by subsequent branch instructions. In typical pipelined implementations if the instruction preceding a branch decision modifies the condition code, then the ALU produces the condition code in the same clock cycle in which the subsequent branch decision is made. If the condition code is instead set by an instruction not immediately preceding the branch decision, the condition code must be read from a condition code register. As such, the ALU must choose to use either the ALU output status signals or the status signals stored in the condition code register. This choice is typically made using a forwarding mux, adding another gate delay to the branch decision for the prior art circuit.